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semiconductor group 149 ? 8 388 608 words by 8-bit organization ? 0 to 70 ?c operating temperature ? fast access and cycle time ras access time: 50 ns (-50 version) 60 ns (-60 version) cycle time: 84 ns (-50 version) 104 ns (-60 version) cas access time: 13 ns ( -50 version) 15 ns ( -60 version) ? hyper page mode (edo) cycle time 20 ns (-50 version) 25 ns (-60 version) ? single + 3.3 v ( 0.3v) power supply ? low power dissipation max. 396 active mw ( hyb 3164805j/t(l)-50) max. 360 active mw ( hyb 3164805j/t(l)-60) max. 504 active mw ( hyb 3165805j/t(l)-50) max. 432 active mw ( hyb 3165805j/t(l)-60) 7.2 mw standby (ttl) 720 w standby (mos) 14.4 mw self refresh (l-version only) ? read, write, read-modify-write, cas-before- ras refresh (cbr), ras-only refresh, hidden refresh and self refresh modes ? hyper page mode (edo) capability ? 8192 refresh cycles/128 ms , 13 r/ 11c addresses (hyb 3164805j/t(l)) ? 4096 refresh cycles/ 64 ms , 12 r/ 12c addresses (hyb 3165805j/t(l)) ? plastic package: p-soj-34-1 500 mil hyb 3164(5)805j p-tsopii-34-1 500 mil hyb 3164(5)805t(l) hyb 3164805j/t(l) -50/-60 hyb 3165805j/t(l) -50/-60 8m x 8-bit dynamic ram (4k & 8k refresh, edo-version) preliminary information
semiconductor group 150 hyb3164(5)805j/t(l)-50/-60 8m x 8 edo-dram this hyb3164(5)805 is a 64 mbit dynamic ram organized 8 388 608 x 8 bits. the device is fabricated in siemens/ibm most advanced first generation 64mbit cmos silicon gate process technology. the circuit and process design allow this device to achieve high performance and low power dissipation. the hyb3164(5)805 operates with a single 3.3 +/-0.3v power supply and interfaces with either lvttl or lvcmos levels. multiplexed address inputs permit the hyb 3164(5)805 to be packaged in a 500mil wide soj-34 or tsop-34 plastic package. these packages provide high system bit densities and are compatible with commonly used automatic testing and insertion equipment.the hyb3164(5)805tl parts have a very low power ?sleep mode supported by self refresh. ordering information pin names type ordering code package descriptions hyb 3164805j-50 on request p-soj-34-1 500 mil dram (access time 50 ns) hyb 3164805j-60 on request p-soj-34-1 500 mil dram (access time 60 ns) hyb 3164805t-50 on request p-tsopii-34-1 500 mil dram (access time 50 ns) hyb 3164805t-60 on request p-tsopii-34-1 500 mil dram (access time 60 ns) hyb 3164805tl-50 on request p-tsopii-34-1 500 mil dram (access time 50 ns) hyb 3164805tl-60 on request p-tsopii-34-1 500 mil dram (access time 60 ns) hyb 3165805j-50 on request p-soj-34-1 500 mil dram (access time 50 ns) hyb 3165805j-60 on request p-soj-34-1 500 mil dram (access time 60 ns) hyb 3165805t-50 on request p-tsopii-34-1 500 mil dram (access time 50 ns) hyb 3165805t-60 on request p-tsopii-34-1 500 mil dram (access time 60 ns) hyb 3165805tl-50 on request p-tsopii-34-1 500 mil dram (access time 50 ns) hyb 3165805tl-60 on request p-tsopii-34-1 500 mil dram (access time 60 ns) a0-a12 address inputs for hyb 3164805j/t(l) a0-a11 address inputs for hyb 3165805j/t(l) ras row address strobe oe output enable i/o1-i/o8 data input/output cas column address strobe write read/write input vcc power supply ( + 3.3v) vss ground
semiconductor group 151 hyb3164(5)805j/t(l)-50/-60 8m x 8 edo-dram pin configuration p-soj-34-1 (500 mil) p-tsopii-34-1 (500 mil)
semiconductor group 152 hyb3164(5)805j/t(l)-50/-60 8m x 8 edo-dram truth table function ras cas write oe row addr col addr i/o1- i/o4 standby h h - x x x x x high impedance read l l h l row col data out early-write l l l x row col data in delayed-write l l h - l h row col data in read-modify-write l l h - l l - h row col data out, data in hyper page mode read 1st cycle l h - l h l row col data out 2nd cycle l h - l h l n/a col data out hyper page mode write 1st cycle l h - l l x row col data in 2nd cycle l h - l l x n/a col data in hyper page mode rmw 1st cycle l h - l h - l l - h row col data out, data in 2st cycle l h - l h - l l - h n/a col data out, data in ras only refresh l h x x row n/a high impedance cas-before- ras refresh h - l l h x x n/a high impedance test mode entry h - l l l x x n/a high impedance hidden refresh read l-h-l l h l row col data out write l-h-l l l x row col data in self refresh (l-version only) h - l l h x x x high impedance
semiconductor group 153 hyb3164(5)805j/t(l)-50/-60 8m x 8 edo-dram block diagram for hyb 3165805j/t(l)
semiconductor group 154 hyb3164(5)805j/t(l)-50/-60 8m x 8 edo-dram block diagram for hyb 3164805j/t(l)
semiconductor group 155 hyb3164(5)805j/t(l)-50/-60 8m x 8 edo-dram absolute maximum ratings operating temperature range..............................................................................................0 to 7 0 ?c storage temperature range.........................................................................................C 55 to 150 ? c input/output voltage..................................................................................-0.5 to min (vcc+0.5,4.6) v power supply voltage....................................................................................................-0.5v t o 4.6 v power dissipation.............................................................................................................. ........1.0 w data out current (short circuit)............................................................................................... ...50 ma note stresses above those listed under ?absolute maximum ratings may cause permanent damage of the device. exposure to absolute maximum rating conditions for extended periods may effect device reliability. dc characteristics t a = 0 to 70 ?c, v ss = 0 v, v cc = 3.3 v 0.3 v, (values in brackets for hyb 3165805j/t) parameter symbol limit values unit note min. max. input high voltage v ih 2.0 vcc+0.3 v 1) input low voltage v il C 0.3 0.8 v 1) output high voltage (lvttl) output ?h level voltage (iout = -2ma) v oh 2.4 C v output low voltage (lvttl) output ?llevel voltage (iout = +2ma) v ol C 0.4 v output high voltage (lvcmos) output ?h level voltage (iout = -100ua) v oh vcc-0.2 - v ouput low voltage (lvcmos) output ?l level voltage (iout = +100ua) v ol - 0.2 v input leakage current,any input (0 v < vin < vcc , all other pins = 0 v i i(l) C 2 2 m a output leakage current (do is disabled, 0 v < vout < vcc ) i o(l) C 2 2 m a average vcc supply current: -50 ns version -60 ns version ( ras, cas, address cycling: trc = trc min.) i cc1 C C 110 (140) 100 (120) ma ma 2) 3) 4) standby vcc supply current ( ras= cas= vih) i cc2 C 2 ma C
semiconductor group 156 hyb3164(5)805j/t(l)-50/-60 8m x 8 edo-dram average vcc supply current, during ras-only refresh cycles: -50 ns version -60 ns version (ras cycling: cas = vih: trc = trc min.) i cc3 C C 110 (140) 100 (120) ma ma 2) 4) average vcc supply current, during hyper page mode (edo): -50 ns version -60 ns version ( ras = v il , cas, address cycling: thpc=thpc min.) i cc4 C C 115 (150) 100 (120) ma ma 2) 3) 4) standby vcc supply current ( ras= cas= vcc-0.2v) i cc5 C 200 a C average vcc supply current, during cas-before- ras refresh mode: -50 ns version -60 ns version ( ras, cas cycling: trc = trc min.) i cc6 C C 110 (140) 100 (120) ma ma 2) 4) self refresh current (l-version only) average power supply current during self refresh. (cbr cycle with tras>trassmin, cas held low, we = vcc-0.2v, address and din=vcc-0.2v or 0.2v) i cc7 C 400 a capacitance t a = 0 to 70 ?c, v cc = 3.3 v 0.3 v, f = 1 mhz parameter symbol limit values unit min. max. input capacitance (a0 to a11,a12) c i1 C5pf input capacitance ( ras, cas, write, oe) c i2 C7pf i/o capacitance (i/o1-i/o8) c io C7pf dc characteristics (contd) t a = 0 to 70 ?c, v ss = 0 v, v cc = 3.3 v 0.3 v, (values in brackets for hyb 3165805j/t) parameter symbol limit values unit note min. max.
semiconductor group 157 hyb3164(5)805j/t(l)-50/-60 8m x 8 edo-dram ac characteristics 5)6) t a = 0 to 70 ?c, v cc = 3.3 v 0.3v , t t = 2 ns parameter symbol limit values unit note -50 -60 min. max. min. max. common parameters random read or write cycle time t rc 84 C 104 C ns ras precharge time t rp 30 C 40 C ns ras pulse width t ras 50 100k 60 100k ns cas pulse width t cas 8 10k 10 10k ns row address setup time t asr 0C0C ns row address hold time t rah 8C10C ns column address setup time t asc 0C0C ns column address hold time t cah 8C10C ns ras to cas delay time t rcd 12 37 14 45 ns ras to column address delay time t rad 10 25 12 30 ns ras hold time t rsh 810Cns cas hold time t csh 45 50 C ns cas to ras precharge time t crp 5C5C ns transition time (rise and fall) t t 1 50 1 50 ns 7 refresh period for hyb3164805 t ref C 128 C 128 ms refresh period for hyb3165805 t ref C 64 C 64 ms read cycle access time from ras t rac C 50 C 60 ns 8, 9 access time from cas t cac C 13 C 15 ns 8, 9 access time from column address t aa C 25 C 30 ns 8,10 oe access time t oea C 13 C 15 ns column address to ras lead time t ral 25 C 30 C ns read command setup time t rcs 0C0C ns read command hold time t rch 0C0C ns11 read command hold time referenced to ras t rrh 0C0C ns11
semiconductor group 158 hyb3164(5)805j/t(l)-50/-60 8m x 8 edo-dram cas to output in low-z t clz 0C0C ns8 output buffer turn-off delay t off 0 13 0 15 ns 12 output buffer turn-off delay from oe t oez 0 13 0 15 ns 12 data to cas low delay t dzc 0C0C ns13 data to oe low delay t dzo 0C0C ns13 cas high to data delay t cdd 13 C 15 C ns 14 oe high to data delay t odd 13 C 15 C ns 14 write cycle write command hold time t wch 8C10C ns write command pulse width t wp 7C10C ns write command setup time t wcs 0C0C ns15 write command to ras lead time t rwl 8C10C ns write command to cas lead time t cwl 8C10C ns data setup time t ds 0C0C ns16 data hold time t dh 7 C 10 C ns 16 read-modify-write cycle read-write cycle time t rwc 111 C 135 C ns ras to we delay time t rwd 67 C 79 C ns 15 cas to we delay time t cwd 30 C 34 C ns 15 column address to we delay time t awd 42 C 49 C ns 15 oe command hold time t oeh 7C10C ns hyper page mode (edo) cycle hyper page mode (edo) cycle time t hpc 20 C 25 C ns cas precharge time t cp 8C10C ns access time from cas precharge t cpa C 27 C 35 ns 7 output data hold time t coh 5C5C ns ras pulse width in hyper page mode t ras 50 200k 60 200k ns ac characteristics (contd) 5)6) t a = 0 to 70 ?c, v cc = 3.3 v 0.3v , t t = 2 ns parameter symbol limit values unit note -50 -60 min. max. min. max.
semiconductor group 159 hyb3164(5)805j/t(l)-50/-60 8m x 8 edo-dram cas precharge to ras delay t rhcp 27 C 35 C ns oe pulse width t oep 7C10C ns oe hold time from cas high t oehc 7C10C ns we pulse width to output disable at cas high t wpz 7C10C ns output buffer turn-off delay from we t wpz 0 10 0 10 ns hyper page mode (edo) read- modify-write cycle hyper page mode (edo) read-write cycle time t prwc 51 C 66 C ns cas precharge to we t cpwd 41 C 49 C ns cas before ras refresh cycle cas setup time t csr 5C5C ns cas hold time t chr 8C10C ns ras to cas precharge time t rpc 5C5C ns write to ras precharge time t wrp 8C10C ns write hold time referenced to ras t wrh 8C10C ns cas-before-ras counter test cycle cas precharge time ( cas-before- ras counter test cycle) t cpt 35 C 40 C ns self refresh cycle ras pulse width during self refresh t rass 100k _ 100k _ ns 17 ras precharge time during self refresh t rps 84 _ 104 _ ns 17 cas hold time during self refresh t chs -50 _ -50 _ ns 17 ac characteristics (contd) 5)6) t a = 0 to 70 ?c, v cc = 3.3 v 0.3v , t t = 2 ns parameter symbol limit values unit note -50 -60 min. max. min. max.
semiconductor group 160 hyb3164(5)805j/t(l)-50/-60 8m x 8 edo-dram test mode write command setup time t wts 10 C 10 C ns 18) write command hold time t wth 10 C 10 C ns 18) ac characteristics (contd) 5)6) t a = 0 to 70 ?c, v cc = 3.3 v 0.3v , t t = 2 ns parameter symbol limit values unit note -50 -60 min. max. min. max.
semiconductor group 161 hyb3164(5)805j/t(l)-50/-60 8m x 8 edo-dram notes: 1) all voltages are referenced to vss. vih may overshoot to vv + 0.2v for pulse widths of < 4ns with 3.3v. vil may undershoot to -2.0v for pulse width < 4.0 ns with 3.3v. pulse width measured at 50% points with amplitude measured peak to dc reference. 2) icc1, icc3, icc4 and icc6 and icc7 depend on cycle rate. 3) icc1 and icc4 depend on output loading. specified values are measured with the output open. 4) address can be changed once or less while ras = vil.in the case of icc4 it can be changed once or less during a hyper page mode cycle ( thpc). 5) an initial pause of 100 s is required after power-up followed by 8 ras-only-refresh cycles, before proper device operation is achieved. in case of using internal refresh counter, a minimum of 8 cas-before- ras initialization cycles instead of 8 ras cycles are required. 6) ac measurements assume tt = 2 ns. 7) vih (min.) and vil (max.) are reference levels for measuring timing of input signals. also, transition times are measured between vih and vil. 8) measured with the specified current load and 100 pf at voh = 2.0 v and vol = 0.8 v. 9) operation within the trcd (max.) limit ensures that trac (max.) can be met. trcd (max.) is specified as a reference point only: if trcd is greater than the specified trcd (max.) limit, then access time is controlled by tcac. 10) operation within the trad (max.) limit ensures that trac (max.) can be met. trad (max.) is specified as a reference point only: if trad is greater than the specified trad (max.) limit, then access time is controlled by taa. 11) either trch or trrh must be satisfied for a read cycle. 12) toff (max.) and toez (max.) define the time at which the outputs achieve the open-circuit condition and are not referenced to output voltage levels. 13) either tdzc or tdzo must be satisfied. 14) either tcdd or todd must be satisfied. 15) twcs, trwd, tcwd, tawd and tcpwd are not restrictive operating parameters. they are included in the data sheet as electrical characteristics only. if twcs > twcs (min.), the cycle is an early write cycle and the i/o pin will remain open-circuit (high impedance) through the entire cycle; if trwd > trwd (min.), tcwd > tcwd (min.), tawd > tawd (min.) and tcpwd > tcpwd (min.) , the cycle is a read-write cycle and i/o pins will contain data read from the selected cells. if neither of the above sets of conditions is satisfied, the condition of the i/o pins (at access time) is indeterminate. 16) these parameters are referenced to cas leading edge in early write cycles and to write leading edge in read-modify-write cycles. 17) when using self refresh mode, the following refresh operations must be performed to ensure proper dram operation: if row addresses are being refresh in an evenly distributed manner over the refresh interval using cbr refresh cycles, then only one cbr cycle must be performed immediatly after exit from self refresh. if row addresses are being refresh in any other manner (ror - distributed/burst or cbr-burst) over the refresh interval, then a full set of row refreshed must be performed immediately before entry to and immediatey after exit from self refresh 18) in a test mode read cycle, the value of trac, taa, tcac and tcpa are delayed by 5 ns from the specified value. these parameters must be adjusted in test mode cycles by adding 5ns to the specified value. associated timings must be adjusted by 5 ns.
semiconductor group 162 hyb3164(5)805j/t(l)-50/-60 8m x 8 edo-dram read cycle row column row valid data out ras cas address we oe i/o (inputs) i/o (outputs) v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol t ras t rc t csh t rad t cas t rp t rah t crp t rsh t rcd t ral t asr t cah t asc t asr t rch t rrh t rcs t aa t oea t clz t cac t oez t odd t cdd t off t dzc t dzo t rac hi z hi z h or l wl1
semiconductor group 163 hyb3164(5)805j/t(l)-50/-60 8m x 8 edo-dram write cycle (early write) ras cas address we oe i/o (inputs) i/o (outputs) v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol . t ras t rc t csh t rad t cas t rp t crp t rsh t rcd t ral t asr t cah t asr t cwl t rwl t wp t asc t wch valid data in t ds t dh hi z column row row t rah t wcs h or l wl2
semiconductor group 164 hyb3164(5)805j/t(l)-50/-60 8m x 8 edo-dram write cycle ( oe controlled write) valid data t rwl t wp t oeh t odd t cwl t dzo t oea t clz t ds t oez t dh t rc v ih v il row t dzc h or l hi-z hi-z column row t asc t rad t ral t cah t rah ras cas address we oe i/o (inputs) i/o (outputs) v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol . t ras t csh t cas t rp t crp t rsh t rcd t asr t asr wl3
semiconductor group 165 hyb3164(5)805j/t(l)-50/-60 8m x 8 edo-dram read-write (read-modify-write) cycle row row t csh t cas t crp t rwc t awd t asr t rp t ras t rah t cah i/o (outputs) v oh v ol v ih v il v ih v il i/o (inputs) oe we v ih v il t asr column t rcd t dh t rsh t rad t cwd t oeh t rwd t rwl t cwl t clz t wp t rcs t aa t oea t ds t dzc t dzo t odd t cac t oez valid data in data out t rac h or l t asc v ih v il v ih v il ras cas address v ih v il wl4
semiconductor group 166 hyb3164(5)805j/t(l)-50/-60 8m x 8 edo-dram hyper page mode (edo) read cycle t rp t rsh t cas t cas t cp t crp t ral t cah t cah t asc t csh t cas t rcd t rah t asr column 2 row data out ras i/o we address cas v ih v il v ih v il v ih v il v ih v il v ih v il h or l v oh v ol oe t ras t crp t asc t hpc t cah t rad t rhcp t asc t rcs t rrh t rch (output) t rac t aa t cac t clz t oea t oes t coh t cac t aa t cpa data out column n column 1 data out t oez t off t cac t aa t cpa 1 2 t coh n wl5
semiconductor group 167 hyb3164(5)805j/t(l)-50/-60 8m x 8 edo-dram hyper page mode (edo) read cycle ( oe control) t rp t rsh t cas t cas t cp t crp t ral t cah t cah t asc t csh t cas t rcd t rah t asr column 2 row data out ras i/o we address cas v ih v il v ih v il v ih v il v ih v il v ih v il h or l v oh v ol oe t ras t crp t asc t hpc t cah t rad t rhcp t asc t rcs t rrh t rch (output) t rac t aa t cac t clz t oea t oes t oez t cac t aa t cpa data out column n column 1 data out t oez t off t cac t aa t cpa 1 2 n t oep t oehc t oea t oep t oehc t oez t oea wl6
semiconductor group 168 hyb3164(5)805j/t(l)-50/-60 8m x 8 edo-dram hyper page mode (edo) read cycle ( we control) t rp t rsh t cas t cas t cp t crp t ral t cah t cah t asc t csh t cas t rcd t rah t asr column 2 row data out ras i/o we address cas v ih v il v ih v il v ih v il v ih v il v ih v il h or l v oh v ol oe t ras t crp t asc t hpc t cah t rad t rhcp t asc t rcs t rrh t rch (output) t rac t aa t cac t clz t oea t oes t whz t cac t aa t cpa data out column n column 1 data out t oez t off t cac t aa t cpa 1 2 n t rch t rcs t wpz t rch t rcs t wpz t whz wl7
semiconductor group 169 hyb3164(5)805j/t(l)-50/-60 8m x 8 edo-dram hyper page mode (edo) early write cycle t rp t rsh t cas t cas t cp t crp t ral t cah t cah t asc t cwl t wcs t wp t wch t csh t cas t rcd t rah t asr t dh t ds t dh t ds column 1 column 2 row addr data in n data in 2 data in 1 column n ras i/o (input) we address cas v ih v il v ih v il v ih v il v ih v il v ih v il h or l v oh v ol oe t ras t crp t asc t cwl t wcs t wp t wch t cwl t wcs t wp t wch t rwl t dh t ds t hpc t cah t rad t rhcp t asc wl8
semiconductor group 170 hyb3164(5)805j/t(l)-50/-60 8m x 8 edo-dram hyper page mode (edo) late write cycle t rp t rsh t cas t cas t cp t crp t ral t cah t cah t asc t csh t cas t rcd t rah t asr column 2 row data in ras i/o we address cas v ih v il v ih v il v ih v il v ih v il v ih v il h or l v oh v ol oe t ras t crp t asc t hpc t cah t rad t asc t rcs (input) t odd t dh data in column n column 1 data in t oeh 1 2 n t wp t rcs t wp wl16 cp t t ds t dh t ds t wp t ds t dh t rcs t cwl t cwl t cwl t rwl t odd t oeh t odd t oeh
semiconductor group 171 hyb3164(5)805j/t(l)-50/-60 8m x 8 edo-dram hyper page mode (edo) read-modify-write cycle t cah t cp t dzc t dzo t rac t cac t clz t rcs t aa t oea t rcd t rad t rah t asr t asc t cas t cas t prwc t cwd t cah t asc t cas t rsh t rp t crp t asr t cah t asc t ral t cwd t rwd t cwl t cwl t cwd t awd t awd t wp t wp t cwl t rwl t awd t wp t odd t oeh t dh t ds t cpa t oez t clz t dzc t aa t cac t oea t ds t oez t dh t oeh t aa t odd t dzc t cpa t oea t clz t ds t dh t oeh t odd ras v ih v il cas v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol we oe address i/o (inputs) i/o (outputs) data in data in data in data out out data data out row column column row t rasp t csh column t cpwd t cpwd wl17
semiconductor group 172 hyb3164(5)805j/t(l)-50/-60 8m x 8 edo-dram ras only refresh cycle t crp t rah t rp t ras t rc t asr t asr t rpc v ih v il v ih v il v ih v il v oh v ol row row hi-z address ras cas i/o (outputs) h or l wl9
semiconductor group 173 hyb3164(5)805j/t(l)-50/-60 8m x 8 edo-dram cas-before- ras refresh cycle t rp t ras t rp t rc t crp t cp t rpc t chr t wrh t wrp t csr t rpc t off t oez t cdd t odd v ih v il v ih v il v ih v il v ih v il v ih v il hi-z h or l ras i/o (outputs) i/o (inputs) oe we cas v oh v ol wl10
semiconductor group 174 hyb3164(5)805j/t(l)-50/-60 8m x 8 edo-dram hidden refresh read cycle ras i/o (outputs) i/o (inputs) oe we address cas t rc t rc t ras t ras t rp t rp t crp t chr t rad t cah t asc t rah t asr t asr t rcs t rrh t aa t dzc t dzo t cac t rac t clz t oez t off t odd t cdd t rcd t rsh t oea v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il t wrp t wrh h or l valid data out row column row hi-z v oh v ol wl11
semiconductor group 175 hyb3164(5)805j/t(l)-50/-60 8m x 8 edo-dram hidden refresh early write cycle ras i/o (output) i/o (input) we address v ih v il v ih v il v ih v il cas v ih v il v ih v il h or l t rc t ras t rcd t rsh t rad t cah t wcs t wch t wp t asr t rah t ds t dh t asr t crp t chr t rp t ras t rc t rp t asc row row valid data hi-z column v oh v ol t wrp t wrh wl12
semiconductor group 176 hyb3164(5)805j/t(l)-50/-60 8m x 8 edo-dram self refresh (sleep mode) t rps t rass t rp t crp t cp t rpc t wrh t wrp t csr t off t oez t cdd t odd v ih v il v ih v il v ih v il v ih v il v ih v il hi-z h or l ras i/o (outputs) i/o (inputs) oe we cas v oh v ol t chs wl13
semiconductor group 177 hyb3164(5)805j/t(l)-50/-60 8m x 8 edo-dram test mode entry cycle t rc t ras t rp t rpc t crp t chr t wth t rpc t rp t cp t csr t wts t cdd t off t oez t odd i/o (outputs) v oh v ol v ih v il v ih v il i/o (inputs) oe we v ih v il cas ras v ih v il v ih v il h or l hi-z address t rah t asr v ih v il row wl15 hi-z
semiconductor group 178 hyb3164(5)805j/t(l)-50/-60 8m x 8 edo-dram cas-before- ras refresh counter test cycle t csr t asr t asc t chr t cp t wrp t ral t cah t rsh t rp t ras t cas t rcs t cdd t cac t aa t wrh t oea t odd t clz t dzc t dzo t oez t off t rwl t cwl t wch t wcs t wrh t wrp t ds t dh v ih v il v ih v il v ih v il v oh v ol v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il ras i/o (inputs) oe we address cas i/o (outputs) i/o (outputs) i/o (inputs) we oe column row data out data in hi-z read cycle: write cycle: t rrh t rch
semiconductor group 179 hyb3164(5)805j/t(l)-50/-60 8m x 8 edo-dram package outlines p-soj-34-1 (500 mil) (plastic small outline j-leaded package) sorts of packing package outlines for tubes, trays etc. are contained in our data book package information. dimensions in mm smd = surface mounted device
semiconductor group 180 hyb3164(5)805j/t(l)-50/-60 8m x 8 edo-dram p-tsopii-34-1 (500 mil) (plastic thin small outline package type ii sorts of packing package outlines for tubes, trays etc. are contained in our data book package information. dimensions in mm smd = surface mounted device

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